I. Field of the Invention
The present disclosure pertains generally to the field of processors, and more specifically to a shared translation look-aside buffer and method.
II. Background
A translation look-aside buffer (TLB) is a cache used to store recently used virtual-to-physical address translations. When a processor needs to access a memory location indicated by a virtual address, it asks the translation look-aside buffer for the corresponding physical address for the memory location. If the translation look-aside buffer contains the given virtual address, it is a “hit” and the processor is provided the corresponding physical address. When the given virtual address is not in the translation look-aside buffer, it is a “miss” and the processor must search or “walk” the page table for the corresponding physical address. The physical address is then provided or “filled” to the translation look-aside buffer. However, in the case of a shared translation look-aside buffer between multiple processor threads, the address translation for another thread may get “evicted” by the present thread. In some critical operating system operations, this may result in severe errors.
Translation look-aside buffer misses may be handled in software or hardware. However, using hardware to fill translation look-aside buffer entries in case of a translation look-aside buffer miss exception requires specialized hardware that is infrequently used. In some processor implementations, shadow registers are used to save some register contents automatically during exception or interrupt handling. Translation look-aside buffer misses may be handled automatically by the hardware, or may cause an exception and be handled by software. Because interrupts, exceptions and translation look-aside buffer misses are infrequent, having dedicated hardware resources is undesirable because of the increase in complexity and a less efficient design.
In some processors, software is used to handle translation look-aside buffer misses. In case of a translation look-aside buffer miss, software is used to walk the page table entries for the virtual-to-physical address translation. In these processors, a translation look-aside buffer is provided for each central processing unit (CPU) or each processing thread to avoid the problem of another processor or thread changing the translation look-aside buffer entries. However, because it is costly and inefficient to provide a translation look-aside buffer per thread, it is also not practicable in some applications.